The present invention in general relates to a semiconductor storage apparatus comprising a SRAM (Static Random Access Memory) memory cell. In particular, this invention relates to the semiconductor storage apparatus for improving soft error resilience.
In recent years, there is an increasing demand for lighter and thinner electronic devices which function at high-speed. At present, a microcomputer must be mounted in such electronic devices. The constitution of the microcomputer requires a large-capacity and high-speed memory. In view of the rapid proliferation of high-performance personal computers, there is a demand for a large-scale cache memory in order to achieve high-speed processing. That is, there is a demand for a high-speed and large-scale RAM which is used by a CPU when executing control programs and the like.
Generally, a DRAM (Dynamic RAM) and an SRAM (static RAM) are used as the RAM. The SRAM is usually used as the section needed for high-speed processing such as the cache memory mentioned above. Two types of SRAM memory cell constitutions are known. The two types are, a high-resistance load type comprising four transistors and two high-resistance elements, and a CMOS comprising six transistors. These days the CMOS SRAM is used more often since it has extremely low current leakage when holding data and is consequently highly reliable.
FIG. 55 is a circuit diagram showing a memory cell of a conventional CMOS SRAM. FIG. 55 shows only the circuit sections of the memory cell which maintain memory, and omits the MOS transistor for access which is needed for reading and writing the memory status. As shown in FIG. 55, the memory cell can be expressed by two inverters INV1 and INV2 which connect an input terminal and an output terminal in complement.
FIG. 56 is a circuit diagram showing the internal circuit constitution of the inverters INV1 and INV2, that is, a MOS inverter circuit. As shown in FIG. 56, each of the inverters INV1 and INV2 comprises one PMOS transistor PM1 and one NMOS transistor NM1. The source of the PMOS transistor PM1 is connected to a power line VDD and the source of the NMOS transistor NM1 is connected to a ground line GND. The drains of the two transistors are connected together. These commonly connected drains form an output terminal OUT. The gates of the two transistors are connected together. These commonly connected gates form an input terminal IN. The inverter function is realized by a CMOS constitution wherein the PMOS transistor PM1 functions as a load transistor and the NMOS transistor NM1 functions as a drive transistor.
The operation of the CMOS inverter circuit shown in FIG. 56 will be explained. When a potential at high logical level (hereafter, xe2x80x9cHxe2x80x9d), i.e. VDD potential, is applied to the input terminal IN, the PMOS transistor PM1 switches OFF and the NMOS transistor NM1 switches ON.
Consequently, the output terminal OUT is electrically connected via the NMOS transistor NM1 to the ground line, and its potential becomes low logical level (hereafter, xe2x80x9cLxe2x80x9d), i.e. GND potential. Conversely, when a potential at logical level xe2x80x9cLxe2x80x9d, i.e. the GND potential, is applied to the input terminal IN, the NMOS transistor NM1 switches OFF and the PMOS transistor PM1 switches ON. Consequently, the output terminal OUT is electrically connected via the PMOS transistor PM1 to the power line, and its potential becomes logical level xe2x80x9cHxe2x80x9d, i.e. the VDD potential. Thus, there is a complementary relationship between the logic of the input and output of the CMOS inverter circuit.
Subsequently, the conventional memory cell shown in FIG. 55 will be explained. The input terminal of the inverter INV1 and the output terminal of the inverter INV2 are connected together, and the output terminal of the inverter INV1 and the input terminal of the inverter INV2 are connected together. Therefore, there is a complementary relationship between the memory nodes NA and NB in FIG. 55.
For instance, when the storage node NA has a potential of logical level xe2x80x9cHxe2x80x9d, the storage node NB is stable at a potential of logical level xe2x80x9cLxe2x80x9d, and vice versa. In this way, the memory cell comprising the inverters has two different stable logical states depending on whether the two storage nodes NA and NB are at the xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d levels, and the logical state of the memory cell is held as one bit of stored data.
The semiconductor storage apparatus comprising the CMOS inverter circuit has extremely good stability and so far there have been no problems regarding noise tolerance. However, in the case of a large-capacity memory formed by integrating a great number of memory cells such as that described above, the memory cell area per bit becomes extremely small, affecting the charge generated when the circuit is struck by ionizing radiation. That is, the storing status of the memory cells is made unstable by the emission of radiation, increasing the possibility of errors such as inverted data storage.
This phenomenon is termed a xe2x80x9csoft errorxe2x80x9d and is caused by xcex1 rays which are emitted from the materials used for packaging and inter connections. A soft error is particularly likely to occur as the power voltage decreases. For this reason, the matter of how to increase tolerance against soft errors is an important issue in recent semiconductor storage apparatuses which are driven at low power.
Various semiconductor storage apparatuses wherein soft-error tolerance is increased by increasing the capacitance of the storage nodes have been proposed. For example, according to the xe2x80x9csemiconductor memory apparatusxe2x80x9d disclosed in Japanese Patent Application Laid-Open No. 9-27046, a capacitor is formed by inserting a thin active region between the storage nodes (i.e. the connections between the gates of the driving transistors and the gates of the load transistors forming the CMOS inverter) and the semiconductor substrate, thereby increasing the capacitance of the storage node sections.
On the other hand, there is a nonvolatile semiconductor storage apparatus comprising a memory cell for SRAM, a transistor for access and several capacitors. In this nonvolatile semiconductor storage apparatus, the capacitance of the storage nodes is an important matter.
According to this nonvolatile semiconductor storage apparatus, the potential is determined by dividing the capacitance of the multiple capacitors and data is written. The relative sizes of the capacitances of the capacitors connected at the nodes is read when the power is switched ON. Therefore, it has been difficult to suitably design the capacitors. Japanese Patent Application Laid-Open No. 62-33392 discloses a xe2x80x9cnonvolatile semiconductor storage apparatusxe2x80x9d in which the capacitors are eliminated by connecting the gate of an MOS transistor having a floating gate to the storage node of the SRAM memory cell instead of the capacitor, thereby forming a nonvolatile memory section.
However, in order to meet demands for a more highly-integrated semiconductor storage apparatus having larger capacity, the constituent elements of the memory cell must be made minute. This leads to the disadvantages that the capacitance of the storage node section becomes even smaller, increasing the possibility of soft errors.
To solve this problem, conventional memory cells such as that disclosed in Japanese Patent Application Laid-Open No. 9-270469 described above must use a specific semiconductor layout pattern in order to increase the capacitance of the storage node sections. The process of redesigning the layout pattern so as to cope with high integration of the memory cell in the future are complex, and there may not be any easy solutions.
According to the xe2x80x9cnonvolatile semiconductor storage apparatusxe2x80x9d disclosed in Japanese Patent Application Laid-Open No. 62-33392 mentioned above, the MOS transistor connected to the storage node of the SRAM memory cell comprises a nonvolatile memory section, and consequently must have a layout enabling a floating gate to be provided. Moreover, the storage state of the floating gate may be altered as a result of the emission of xcex1 rays. This xe2x80x9cnonvolatile semiconductor memory apparatusxe2x80x9d cannot simultaneously realize the nonvolatile memory function and soft error countermeasures, nor is it intended to do so.
It is an object of this invention to obtain a semiconductor storage apparatus in which soft error countermeasures have been implemented, that is, to increase the capacity of storage nodes by providing a PMOS transistor and NMOS transistor having established processes of design and manufacturing to an SRAM memory cell and connecting the gates of the added MOS transistors to the storage nodes.
In the semiconductor storage apparatus according to one aspect of this invention, load transistors such as, for example, diode-connected MOS transistors are connected to the drains of a first NMOS transistor and a second NMOS transistor NM1, thereby obtaining an SRAM memory cell. The drain of a first PMOS transistor and the gate of a second PMOS transistor are connected to a first node which is a storage node. The drain of the second PMOS transistor and the gate of the first PMOS transistor are connected to a second node which is another storage node. The gate capacity and drain capacity of the PMOS transistors can be added to the storage nodes.
In the semiconductor storage apparatus according to another aspect of this invention, shared diffusion regions for providing the drains and sources of the first, third, fifth and seventh NMOS transistors and connecting them together can easily be provided therebetween. Furthermore, shared diffusion regions for providing the drains and sources of the second, fourth, sixth and eighth NMOS transistors and connecting them together can easily be provided therebetween.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.